| 1. | At last , the layout is verified with cadence verification tools , dracula . drc ( design rule cherker ) and lvs ( layout versus schematic ) have been done successfully , which improve the feasibility of the layout design . so the whole ic design flow , from the front end to the back end of a circuit design , is completed
接着应用无锡上华标准0 . 6umcmos工艺提供的元器件模型参数进行了电路仿真,并根据尺寸设计规则设计了整体电路的的版图,最后运用cadence中的版图验证工具集dracula对电路版图成功地进行了drc ( designrulecherker ) 、 lvs ( layoutversusschematic )验证,证明了电路版图设计的可行性,完成了ic设计从前端到后端的设计流程。 |
